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Mid Level ASIC Library Validation Engineer

Company: Boeing
Location: Gardena
Posted on: September 4, 2020

Job Description:

At Boeing, we are all innovators on a mission to connect, protect, explore and inspire. From the seabed to outer space, youll learn and grow, contributing to work that shapes the world. Find your future with us. Boeings Solid State Electronics Development organization (SSED) within the Boeing Research and Technology (BR&T) organization performs microelectronics technology development and design for aerospace systems.We develop digital, analog, and RF Systems on Chip (SoCs) for radar, navigation, electronic warfare, communications, processing, and other electronic systems. These systems are used on Boeing airborne, terrestrial, and satellite platforms. Designs are implemented with state of the art semiconductor process technologies including CMOS, GaAs, GaN, and SiGe. SSED uses external wafer fabrication but performs design (architecture, RTL, synthesis, circuits, physical design, verification, packaging and test) in house. SSED has numerous microelectronics projects, funded both by internal Boeing customers and external Government Science and Technology (S&T) customers. SSEDs large staff of microelectronics engineers conduct research and designs microelectronics hardware in support of these projects.In this role you will be responsible for generation, modification, validation, release, updating, management of all library views typically needed to support advanced node ASIC design flows utilizing digital EDA tools. Develop an automated test suite with sample ASIC block and SOC level designs that validate the libraries with all tools used throughout the design flow. Produce libraries that exhibit correct function, timing, power, noise, signal integrity and meet all physical validation checks like DRC/LVS. Interact effectively with internal design teams and outside vendors to prove out releases, flow, solve bugs, and improve usability.The Solid State Electronics Development organization is looking to hire a Mid Level ASIC Library Validation Engineer Position Responsibilities:

  • Generation, modification, validation, release, updating, management of all library views typically needed to support advanced node ASIC design flows utilizing digital EDA tools
  • Develop an automated test suite with sample ASIC block and SOC level designs that validate the libraries with all tools used throughout the design flow
  • Produce libraries that exhibit correct function, timing, power, noise, signal integrity and meet all physical validation checks like DRC/LVS
  • Interact effectively with internal design teams and outside vendors to prove out releases, flow, solve bugs, and improve usabilityBasic Qualifications (Required Skills/Experience):
    • This position requires the ability to obtain a US Security Clearance for which the US Government requires US Citizenship.
    • Bachelor''s, Master''s or Doctorate of Science degree from an accredited course of study, in engineering, computer science, mathematics, physics or chemistry
    • 2+ years of experience in the design/development or validation of integrated circuitsPreferred Qualifications (Desired Skills/Experience):
      • Previous experience with library generation and automated validation approaches
      • Deep understanding and previous experience with front to back end ASIC design and tool flow
      • Deep technical knowledge and experience with physical design and validation, spice simulation
      • Strong understanding of front-to-back-end tool flow and how the QA of a PDK can affect various tools
      • Strong knowledge of circuit design languages - Verilog, VHDL, SystemVerilog
      • Strong Knowledge of EDA-centric programming languages Perl, Python, TCL, Bash, C++
      • Familiar with EDA standards used in cell/library development and modeling (LEF, DEF, UPF, OA, etc)
      • Knowledge and previous use of these widely used EDA tools: Library characterization and validation (Silicon Smart, Crossfire, Liberty NCX), physical design (ICC2, Innovus, DC, Genus), transistor level extraction and layout (Cadence Virtuoso and HSPICE), timing, power, IR drop, noise and integrity analysis (Primetime, Tempus, Redhawk), front-end analysis tools (Spyglass, VCLP, Formality, Galaxy Constraints Analyzer), simulation tools (Modelsim, VCS, NCSIM)
      • Demonstrated track record as a high performance team member
      • Excellent verbal and written communication ability
      • Active security clearanceTypical Education/Experience: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 5 or more years'' related work experience or an equivalent combination of technical education and experience (e.g. PhD, Master+3 years'' related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.Relocation: Relocation assistance is available for eligible candidatesDrug Free Workplace: Boeingis a Drug Free Workplace where post offer applicants and employees are subject to testing for marijuana, cocaine, opioids, amphetamines, PCP, and alcohol when criteria is met as outlined in our policies.Employee Referral: Referral to this job is eligible for bonusAdditional Information: All information provided will be checked and may be verified.Please apply as soon as possible for this role as recruitment may commence before the end date.Experience Level
        Individual Contributor
        Contingent Upon Program Award
        No, this position is not contingent upon program awardby Jobble

Keywords: Boeing, Gardena , Mid Level ASIC Library Validation Engineer, Engineering , Gardena, California

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